1. Related Applications
This invention is related to Dynamic Video Ram Incorporating on Chip Vector/Image Mode Line Modification, Ser. No. 07/277,687, filed Nov. 29, 1988 and Dynamic Video Ram Incorporating on Chip Line Modification, Ser. No. 07/277,637, filed Nov. 29, 1988.
2. Field of the Invention
The invention relates to a dual ported, dynamic memory designed for use in raster scan graphic applications and, more particularly, to a high density dynamic video RAM incorporating on a single integrated circuit chip a single random port clock for operation of the random port side of the RAM.
3. Statement of the Problem
With the cost per bit of semiconductor memory and the price of computer systems dropping, personal work stations and other computer systems using graphics such as CAD/CAM systems are becoming more readily available. A crucial component in such systems is the dynamic video RAM which supports the graphics applications.
Conventional dynamic video RAMS, available on multichips, have a random port and a serial port enabling a computer to access the dynamic video RAM through the random port and enabling the serial port to deliver the necessary graphics information to drive, for example, a color monitor.
In designing dynamic video RAMS, several features are of critical importance.
First, it is important to package the video RAM on a single integrated circuit chip while minimizing the number of external pins from the chip. Secondly, it is important to maximize the memory contained on the chip. Third, it is important to perform as many of the modification operations on chip, rather than having off chip hardware perform these operations at a slow rate off the chip. Fourth, it is important to maximize the addressing capabilities of the data stored within the chip. The number of clock inputs controlling the random port of the video RAM leads to complexity and slower speed.
The following patents are representative of issued patents involving the use of clocks in dynamic RAMs commercially available.
The 1987 patent issued to Novak, et al. (U.S. Pat. No. 4,688,197) sets forth a video computer system having a RAM chip with a shift register connected to its serial output terminal which is actuated by a first clock and a second clock is utilized to load the serial chip register.
The 1987 patent to Redwine et al. (U.S. Pat. No. 4,689,741) pertains to the same invention as the '197 patent but provides for coupling of data between column lines and the chip register.
The 1985 patent to Bruce (U.S. Pat. No. 4,546,451) sets forth a dynamic RAM which permits "page mode" addressing. While Bruce shows a graphics controller device (GDC) clock, this clock is delivered from the RAM chip to the separate GDC. More importantly, the separate GDC must provide the load, count enable and other control signals directly to the RAM chip.
The 1987 patent to Thaden (U.S. Pat. No. 4,665,495) sets forth a single chip dynamic RAM controller and CRT controller system arrangement. This invention minimizes the control circuit of prior systems thus eliminating potential bottle necks at the RAM by utilizing a single controller. A related patent also issued to Thaden et al. is U.S. Pat. No. 4,656,596. The RAM of Thaden resides on a chip separated from the controller chip and the control signals are sent to the RAM.
The 1987 patent to Voss (U.S. Pat. No. 4,646,270) sets forth a video graphic dynamic RAM having the capability of serially reading out data at a high rate of speed while performing standard RAM operations.
In the above patents, no provision is made for utilizing a single clock on the random port side of the RAM to control the operation of the RAM including the loading of information into the address and data registers, the operation of the RAM and the modification of the information in the RAM.
4. Solution to the Problem
The present invention provides a solution to the above problem. Under the teachings of the present invention, a single clock pulse drives an internal state machine to provide the control pulses thereby minimizing the number of signal paths to and from the chip while providing for a faster operation.